Design of a 3780-point IFFT processor for TDS-OFDM
Zhixing Yang, Yupeng Hu, Changyong Pan, Lin Yang · IEEE Transactions on Broadcasting · 2002
This correspondence presents a design of 3780-point IFFT processor for TDS-OFDM terrestrial DTV transmitter using FPGA. It demonstrates the algorithm design and error analysis of the processor, which can achieve a throughput of 7.56M complex IFFT operations per second. This design meets the signal-to-quantization noise ratio requirement of the TDS-OFDM system. It consists of two FPGA and one dual-port RAM. The data stream pipeline algorithm is implemented.