SLS-a fast switch-level simulator (for MOS)
Z. Barzilai, D.K. Beece, Leendert M. Huisman, V. Iyengar, Gabriel M. Silberman · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1988
SLS, a large-capacity, high-performance switch-level simulator developed to run on an IBM System/370 architecture is described. SLS uses a model which closely reflects the behavior of MOS circuits. The high performance is the result of mixing a compiled model with the more traditional approach of event-driven simulation control, together with very efficient algorithms for evaluating the steady-state response of the circuit. SLS is used for design verification/checking applications and for estimating fault coverage.>