VLSI design and verification of the Imagine processor
Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jae‐Eun Namkoong, Brian Towles · 2003
The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford University and Texas Instruments in a 1.5 V 0.15 /spl mu/m process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design a high-performance media processor in a modern ASIC flow.