Testing and testable designs for one-time programmable FPGAs
Tong Liu, Wei Kang Huang, F.J. Meyer, Fabrizio Lombardi · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2000
We present a methodology for production-time testing of one-time programmable field programmable gate arrays (FPGAs) such as those manufactured by Actel. The methodological principles are based on connecting the uncommitted modules (sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays, similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions for constant testability (C testability). Two design approaches are proposed. Features such as testing time and hardware requirements (measured by the number of cycles and additional transistors and primary input-output pins) are analyzed. We show that the proposed designs require considerably less testing time than a previous technique based on scan. The proposed approaches require 8+n/sub f/ vectors for testing the Actel FPGAs, where n/sub f/ is the number of flip-flops in a row. Hardware overhead for the testing circuitry is also analyzed.