Critical path selection for performance optimization
Hsi-Chuan Chen, David H. C. Du, Li-Ren Liu · 1991
In this paper we study the problem of selecting a set of paths to optimize the performance of a circuit.We assume that gate resizing is the optimizing technique used to reduce the delay of a circuit.That is, during the optimization process the topology of a circuit remains the same and the gate delays are reduced.The objective of the path selection problem is to select as few paths as possible so that when the delays of all selected paths are shortened, the delay of the optimized circuit is guaranteed to meet its performance requirement.We first propose an input vector oriented path selection algorithm.Due to the fact that the input vector oriented algorithm may be not feasible for complex designs with many input pins, we have designed and developed a path oriented algorithm.For some ISCAS circuits, less than 10% of the long paths are selected by our path oriented algorithm.