A novel biasing technique for addressable parametric arrays
Brad D. Smith, Uma Annamalai, Alexandre Arriordaz, V. Kolagunta, Jeff Schmidt, Mehul D. Shroff · 2008
Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that removes the drain-source bias from these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted more than a two-decade drop in parasitic leakage of the array. Experiment data performed on a 90 nm technology confirmed this improvement.