Detecting redundant accesses to array data
Elana D. Granston, Alexander V. Veidenbaum · 1991
Alleviating memory access delays is crucial to harnessing the potential of hierarchical-memory, highperformance systems, especially vector and paral!el systems.In typica!numerics!applications, a significant portion of global memory data -lrafic arises from accesses to blocks of array elements or regions.Memory access delays due to such trafic can be reduced by using compile-time information to detect when iocal data can be reused, thereby eliminating redundant global memory accesses.In this paper, we present a compile-time algorithm that applies combined flow and dependence analysis to programs with vector and paraL lel constructs to detect such redundancies across loops nests, and in the presence of conditionals.We also show how this information can be used to eliminate redundancies.