Generating VHDL-A—like models using ABSynth
Vincent Moser, Hans Peter Amann, Pascal Nussbaum, Fausto Pellandini · reroDoc Digital Library · 1995
A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.