Register-constrained address computation in DSP programs
A. Basu, Rainer Leupers, Peter Marwedel · 1998
This paper describes a new code optimization technique for digital signal processors (DSPs). One important characteristic of DSP algorithms are iterative accesses to data array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). We present a heuristic technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for array address computations in a program loop. 1 1 Introduction DSPs are a special class of embedded processors, which show highly specialized instruction sets and pose challenges both to compilers and assembly programmers. Many of today's C compilers for DSPs have been shown to produce code of poor quality. In order to overcome this problem, new DSP-specific code optimization techniques are required. In DSP algorithms frequent references to elements of data arrays are very common. Mostly, such array elements are iteratively a...