A Software-Based Method for Test Vector Compression in Testing System-on-a-Chip
Satyendra N. Biswas, SUNIL RANJAN DAS · Conference proceedings - IEEE Instrumentation/Measurement Technology Conference · 2006
A new software-based hybrid test vector compression method for testing system-on-a-chip (SOC) using an embedded processor is presented in this paper. In the proposed approach, a software program is first loaded into the on-chip processor memory core together with the compressed test data set. In order to reduce on-chip storage as well as testing time, the large volume of test data input is compressed in a hybrid fashion before being downloaded into the processor. The method combines a set of adaptive coding techniques for the required test data compression. The compression program, however, need not be loaded into the embedded processor, since only the decompression of test data is necessary for application by the automatic test equipment (ATE). Most importantly, this software-based hybrid scheme requires minimal hardware overhead, while the on-chip embedded processor core can be reused for normal operation after the testing is completed. In the paper, only the compression part of the technique is presented, and the efficiency of the suggested hybrid approach is demonstrated through simulation experiments on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits