A scalable multistage packet switch for terabit IP router based on deflection routing and shortest path routing
Hiroaki Morino, Thai Thach Bao, Nguyen Hoaison, Hitoshi Aida, Tadao Saito · 2003
According to the growth of the Internet, an IP (Internet protocol) router with capacity of terabit/s is required in the near future. To achieve high capacity, the switch fabric should handle many pairs of input ports and output ports. For this purpose, a multistage network switch is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage networks have the advantage of hardware simplicity since the switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, the required amount of hardware is reduced compared with the conventional switch based on the deflection routing principle. A circuit of 8 /spl times/ 8 variable length packet switch element is designed on FPGA, and the required amount of hardware to realize a 64 /spl times/ 64 multistage network is calculated. It is shown that the 64 /spl times/ 64 switch will be implemented within one LSI chip, and that a 10 Tbit/s switch is realized by two-stage interconnection of the LSI chips.