Real-time scheduling in heterogeneous dual-core architectures
Kwang-Sik Kim, Dohun Kim, Chanik Park · 2006
With high computational application, embedded systems are becoming more complex. To achieve high performance in the midst of increased complexity, dual-core SoC (system-on-chip) is used. Of many dual-core architectures, a general purpose CPU and DSP are most widely used. But only a few scheduling policies for this heterogeneous architectures exist to guarantee real-time character. This paper discusses scheduling policy for heterogeneous dual-core architectures. We explore the problem of previous scheduling policy (Gai et al., 2002) based on DPCP (distributed priority ceiling protocol) (Rajkumar et al., 1988; Saewong et al., 1999; Sha et al., 1990) and provide a solution of strict schedulability bound model.