Error catch and analysis for semiconductor memories using march tests
Chi Feng Wu, Chih-Tsun Huang, Chih Wea Wang, Kuo-Liang Cheng, Cheng‐Wen Wu · 2000
We present an error catch and analysis (ECA) system for semiconductor memories. The system consists of a test algo-rithm generator called TAGS, a fault simulator called RAM-SES, and an error analyzer (ERA). We use TAGS to generate a set of test algorithms of different lengths and diagnostic resolu-tions for the memory under test, and use RAMSES to generate the March dictionary for each test algorithm. With the March dictionaries, ERA is able to support March algorithms for easy diagnosis of faulty RAMs. Legacy test algorithms also can be reused. When integrated with a RAM tester, our ECA system can generate RAM bitmaps that are similar to the RAM layout. The bitmaps provide detail information about the error loca-tions and faults causing the errors. Based on the information, diagnosis of the RAM chips for yield and reliability improve-ment can be done more easily. 1.