Graph algorithms for clock schedule optimization
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli · International Conference on Computer Aided Design · 1992
Performance driven synthesis of sequential circuits relies on techniquessuch as optimal clocking, retiming and resynthesis. In this paper we address the optimal clocking problem and demonstrate that it is reducible to a parametric shortest path problem. We use constraints that take into account both the short and long paths. The main contributions are effrcient graph algorithms to solve the set of constraints necessary for correct clocking.