A novel low power 16×16 content addressable memory using PAL
Gnanadhas Josemin Bala, J. Raja Paul Perinbam · 2005
This paper presents a novel low power content addressable memory (CAM) using pass transistor adiabatic logic (PAL). The PAL CAM uses adiabatic principle in the read, write and compare operations. The SPICE simulation of 16/spl times/16 CAM indicates around 95% of power saving at 10MHz operating frequency compared to conventional design. The circuits are designed using 0.6/spl mu/m CMOS technology.