A high performance CMOS programmable logic core
Yi Han, L. McMurchie, Carl Sechen · 2004
Programmable logic cores (PLCs) have become available for systems on a chip (SOCs). We describe a novel highspeed PLC architecture. By combining a high-performance dynamic logic style (output prediction logic or OPL), wired-OR structures, a unidirectional routing flow and a product-term-based structure, this architecture achieves an average speedup of 5.7 times over commercial look-up-table (LUT) based architectures using static CMOS. Experimental results for a prototype block fabricated in the TSMC 0.18 /spl mu/m/1.8 V CMOS process are presented.