Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window
Y. Ahn, S. Cheong, Dongjin Lee, Sung Woo Kim, D. Park, B.-I. Ryu, Jeong Dong Choe, Jinseok Lee, Dong-Uk Choi, E. Cho, B. Choi, S.-H. Lee, S.‐K. Sung, C.-H. Lee · 2006
This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure