A RISC controlled motion estimation processor for MPEG-2 and HDTV encoding
D. Charlot, J.-M. Bard, B. Canfield, C. Cuney, A. Graf, Alain Pirson, Detlef Teichner, F. Yassa · 2002
Describes the architecture of a hierarchical motion estimation processor, with respect to the MPEG-2 encoding standard. This processor can also be used in HDTV applications. The motion estimation processing is in 2 steps: first full-pixel then half-pixel. Several modes are possible, depending on the image types (I, P or B-MPEG terminology, frame based or field based). A decision is taken in this processor to choose the best mode. The architecture is based on a RISC controller, external DRAMs to store anchor frames and specific hardware for processing the distortions. The architecture was chosen to achieve high performance, programmability and high memory bandwidth.