An FPGA implementation of 30Gbps security module for GPON systems
Truong Quang Vinh, Ju-Hyun Park, Young-Chul Kim, Kwang-Ok Kim · 2008
GPON systems require gigabit throughput data encryption for security and privacy. This paper presents an implementation of very high speed security module for GPON on Virtex4 FPGA. The security module supports payload encryption with constant delay by using counter mode AES algorithm. Our design of AES has three advanced features: composite field arithmetic SubByte, efficient MixColumn transformation, and On-the-Fly Key-Scheduling. Full-pipelined architecture is employed for the AES architecture in order to achieve the high performance for security module. The experiment shows that the proposed architecture can achieve a throughput of 30Gbits/s on a Xilinx Virtex-4 VLX100-12 device. The performance of our design is well suitable for encryption applications of GPON systems.