Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme
Jer Min Jou, Yeu-Horng Shiau, Chin-Chi Liu · 2002
In this paper, two efficient VLSI architectures for the biorthogonal wavelet transform are proposed. One is constructed by the filter bank implementation and another is constructed by the lifting scheme. In the filter bank implementation, due to the symmetric property of the biorthogonal wavelet transform, the proposed architecture uses fewer multipliers than the orthogonal wavelet transform. We also adopt the polyphase decomposition to speed up the processing by a factor of 2. In the lifting scheme implementation, the pipeline design style is adopted to optimise the architecture. Both of the proposed VLSI architectures have advantages of lower implementation complexity, faster computation time, and the inverse DWT has the same architecture as the forward DWT. Finally, the architecture constructed by the lifting scheme is implemented in a single chip on a 0.35 /spl mu/m 1P4M CMOS technology, and its area and working performance are 5.005/spl times/5.005 mm/sup 2/ and 50 MHz, respectively.