A pipeline parallel architecture for a fuzzy inference processor
Giuseppe Ascia, Vincenzo Catania · 2002
The paper presents the architecture of a VLSI processor for applications based on fuzzy logic. The main features of the architecture are: a pre-computation phase of the positive degree of truth of the antecedent with fuzzy inputs; a detection phase of the rules positive degree of activation, parallelism in some phases of inference which is split into a sequence of pipeline stages. The processing speed is up to 16.7 MFLIPS for inferences with 64 rules with 4 linguistic variables.