NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Jeremy Chan, Sri Parameswaran · 2008
Networks-on-Chip (NoC) have been widely proposed as the future communication paradigm for use in next-generation System-on-Chip. In this paper, we present NoCOUT, a methodology for generating an energy optimized application specific NoC topology which supports both point-to-point and packet-switched networks. The algorithm uses a prohibitive greedy iterative improvement strategy to explore the de-sign space efficiently. A system-level floorplanner is used to evaluate the iterative design improvements and provide feedback on the effects of the topology on wire length. The algorithm is integrated within a NoC synthesis framework with characterized NoC power and area models to allow accurate explo-ration for a NoC router library. We apply the topology generation al-gorithm to several test cases including real-world and synthetic com-munication graphs with both regular and irregular traffic patterns, and varying core sizes. Since the method is iterative, it is possible to start with a known design to search for improvements. Experimental re-sults show that many different applications benefit from a mix of “on chip networks ” and “point-to-point networks”. With such a hybrid network, we achieve approximately 25 % lower energy consumption (with a maximum of 37%) than a state of the art min-cut partition based topology generator for a variety of benchmarks. In addition, the average hop count is reduced by 0.75 hops, which would significantly reduce the network latency. 1.