Multiprocessor cache simulation using hardware collected address traces
A.W. Wilson · 2002
An evaluation is presented of the performance of large private caches for multiprocessors using hardware-collected address traces. The traces are 14-million memory references in length and are collected from one processor of a multiprocessor in real time. Both uniprocessor performance and multiprocessor time-sliced performance are simulated. The effects of cache size for large caches, process migration, and cache coherency on hit ratio and bus traffic are measured. Conclusions regarding the benefits of large private caches in a time-shared multiprocessor environment are reached.>