Research and Design of Low Power Consumption Testing Generator for Integrated Circuits
Yi Wang · 2010
In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies of low power consumption are summarized. In order to reduce the switching activity rate of internal nodes in circuit-under-test and raise the correlation between testing vector, the Random Single Input Change (RSIC)test theory is introduced. It can reduce the switching activity rate of nodes in the circuit-under-test to realize low power consumption during testing without lossing fault coverage, especially suitable for BIST of digital VLSI.