Design of a CMOS buffered switch for a Gigabit ATM switching network
N. Mirfakhraei · IEEE Journal of Solid-State Circuits · 1995
This paper presents the implementation and design of a gigabit ATM Switch element used in a broadcast ATM switching network supporting 600 Mb/s link rates. The system is designed to operate at the clock speed of 100 MHz. The design of the switch element is developed to fabricate prototype chips using 1.2 /spl mu/ CMOS VLSI technology. The network is constructed with a 256-port Benes topology and the switch element consists of nine identical data slices, and a global controller. Each data slice uses 48 shared buffers. The controller determines which buffer cells are to be sent to the outputs based on its internal contention resolution process. This process is carried out by an arbitration circuit and the decision is made by a buffer control circuit. The controller also generates grant flow control through the network.>