Neuro chips with on-chip back-propagation and/or Hebbian learning
Toshihide Shima, Taiki Kimura, Yukio Kamatani, Tetsuro Itakura, Yuhzo Fujita, Takuya Iida · IEEE Journal of Solid-State Circuits · 1992
A layered neural net realized with two chips is described. One chip implements 24*24 synapses, a local weight control mechanism, and quantized +or-1 LSB, both momentum and weight update schemes. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics verifying the implemented techniques are given.>