Systolic array architecture of Applebaum-Howells array
M. Ueno, K. Kawabata, Takatoshi Morooka · 2003
A systolic array architecture for the Applebaum-Howells array is presented. The proposed architecture uses the preprocessor technique; the overall array consists of a preprocessor and an Applebaum-Howells processor. Assuming that the Gram-Schmidt processor is used as the preprocessor, it is shown that the orthogonality among the Gram-Schmidt processor outputs can remove the global feedback loop needed in the conventional Applebaum-Howells processor, which prevents the array from being used in systolic array implementation, and that the Applebaum-Howells array can be efficiently implemented by using the systolic array architecture.>