A high-performance double precision accumulator
Krishna K. Nagar, Jason D. Bakos · 2009
The accumulation operation Anew= Aold+ X is required for many numerical methods. However, when using a floating-point adder with pipeline latency ¿, the data hazard that exists between Anewand Aoldcreates design challenges for situations where inputs must be delivered to the accumulator at a rate exceeding 1/¿. Each of the techniques proposed to address this problem requires either static data scheduling or overly complex micro-architectures having multiple adders, a large amount of memory, or control overheads that force the accumulator to operate at a diminished speed relative to the adder on which it is based. In this paper we present a design for a double precision accumulator that achieves high performance without the need for data scheduling or an overly complex implementation. We achieve this by integrating a coalescing reduction circuit within the low-level design of a base-converting floating-point adder. When implemented on our Virtex-2 Pro 100 FPGA, our design achieves a speed of 170 MHz.