A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications
Minhyeok Shin, Hanho Lee · 2008
In this paper, we present a novel high-speed low-complexity four data-path 128-point radix-24FFT/IFFT processor for high-throughput MB-OFDM UWB systems. The high radix radix-24multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. A method for compensating the truncation error of fixed-width Booth multipliers with a Dadda reduction network is also employed, which maintains the input and output at 10-bit width with 33dB SQNR. This method leads to reduction of truncation errors compared with direct-truncated Booth multipliers. The proposed FFT/IFFT processor has been designed and implemented with 0.18-μm CMOS technology and a supply voltage of 1.8V. The proposed four-parallel FFT/IFFT processor has a throughput rate of up to 1.8 Gsample/s at 450 MHz while requiring much smaller hardware complexity.