A new built-in TPG method for circuits with random pattern resistant faults
Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitrios Nikolos, Spyros Tragoudas · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2002
The partition of the inputs of a circuit under test (CUT) into groups of compatible inputs reduces the size of a test pattern generator and the length of the test sequence for built-in self-test (BIST) applications. In this paper, a new test-per-clock BIST scheme is proposed which is based on multiple input partitions. The test session consists of two or more phases, and a new grouping is applied during each test phase. Using the proposed method a CUT can be tested at-speed and complete fault coverage (100%) is achieved with a small number of test vectors and small area overhead. Our experiments show that the proposed technique compares favorably to the already known techniques.