A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability
D. Reese, E. Chun, S.D. Cheung, E. Lau, M. Chu, G. Liang, Nghia Van Tran, Brad Vest, R. Smolen, Minchang Liang, S. Sekariapuram, B. Nouban, M. Wong, J. Costello, J. Turner · 2002
The methods and circuits used in the design of a high density, high performance, power efficient, complex PLD are discussed. The EPM9560A is the first member of the third generation MAX 9000 family. Developed on a 0.5 /spl mu/m triple layer metal process, significant improvements in die size, performance, and power have been achieved over the previous generations. Circuit enhancements and design methodologies resulting in better performance are discussed. Analysis methods used in the design of a 560 macrocell PLD with a die size of 99.9 Kmil/sup 2/ and a propagation delay under 7 ns are also discussed.