AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator
K. Murale, Stephan Hildebrandt, Per Bojsen, A. Urzua · 2008
Processors are verified for architectural correctness with instruction set simulators. Traditionally, this verification is done at the full-chip level with the focus on high-level register/memory correctness at each instruction execution. This approach is effective in a full-chip environment with all units in place so a test can be run from beginning to end. At the unit level, running a test means various functionalities of other units need to be filled in by the testbench. The key to accomplishing this in unit level lies in identifying the main flows in fetch, execution, and load/store memory operations, then modeling these correctly. This testbench can then be used at unit level and still verify many full-chip feature sets and pave the way for effective bring-up of full-chip verification with minimal delay. For this, the unit-level verification is done in a framework of a full-chip-like simulation environment with testbench providing stimulus from an AMD64-directed or other executable random test, and a testbench back-end that is tied into an instruction set simulator guaranteeing program order execution with correct test termination. Our back-end execution machine is a combination of testbench interfacing into design at the macro architectural level and an API into an x86-instruction set simulator to get register/memory status update as instructions are stepped. This approach opens up thousands of legacy tests that are normally run in full-chip to run in unit level and be further complemented by executable random streams generated by exercisers.