VLSI implementation of a functional neural network
Dimokritos Panagiotopoulos, Sandeep Kumar Singh, R.W. Newcomb · 2002
The VLSI implementation of a two-hidden layer discretized functional artificial neural network (FANN) has been demonstrated. A chip-set has been defined that implements the FANN, while it allows for expandability in the number of its inputs and outputs, as well as the number of neurons and connections in each hidden layer. Use of current-mode circuitry has resulted in compact multiplication circuitry and efficient manipulation of summation. The components (multiplier, exponential amplifier, analog memory cell) of the FANN have been implemented successfully, through MOSIS, using BiCMOS technology.