Rxiensing scan chains for test pattern decompression
Rainer G. Dorsch, Hans-Joachim Wunderlich · 2005
The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester: The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper; while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.