An efficient representation for formal synthesis
Christian Blumenröhr, Dirk Eisenbiegler · International Symposium on Systems Synthesis · 1997
In the last years, performing synthesis by logical refinement has become an interesting alternative towards post-synthesis verification. This paper gives a case study about the complexity of formal synthesis programs within a given calculus. For a simple synthesis step, it is discussed, how one can efficiently implement circuit transformations with respect to the complexity of the logical transformations of the underlying calculus.