Memory hierarchy design for Jetpipeline: to execute scalar and vector instructions in parallel
T. Sasaki, Takuya Nakaike, Ken Takano, M. Katahira, Hiroaki Kobayashi, Tadao Nakamura · 2002
Superscalar and VLIW architectures are based on instruction level parallelism (ILP), which ideally achieve high performance to execute multiple instructions in parallel. However, the system performance is restricted because of the Von Neumann bottleneck. Therefore, the memory hierarchy design is very important in this kind of architecture. We have proposed a computer architecture named Jetpipeline, which can execute both vector and scalar instructions in parallel. To make full use of the computing ability of Jetpipeline, the paper presents the memory hierarchy design for Jetpipeline and evaluates the effect of the design on the system performance of Jetpipeline through simulations.