A ROM-less DDFS using a nonlinear DAC with an error compensation current array
Chua‐Chin Wang, Chia-Hao Hsu, Tuo-Yu Yao, Jianming Huang · 2008
This paper presents the architecture and the circuit implementation of a direct digital frequency synthesizer (DDFS) with error compensation. The straight line approximation method with a 10-bit amplitude resolution is adopted in this work. The proposed technique replaces conventual ROM-based methods with a nonlinear digital-to-analog converter (DAC) to generate the sinusoid. The overall power dissipation as well as hardware complexity can be significantly reduced. This proposed DDFS is implemented using a standard 0.35 mum CMOS technology. The maximum power dissipation is 3.37 mW at the clock rate of 250 MHz. The chip area is 2.04 mm2. The spurious free dynamic range (SFDR) is 63.22 dBc at a 3 MHz output.