On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Gautam Hazari, Madhav P. Desai, H. Kasture · 2007
Today, VLSI systems for computationally demanding applications are being built as systems-on-chip (SoCs) with a distributed memory subsystem which is shared by a large number of processing elements. The memory sub-system is a potential performance bottleneck in the system. In this paper, the authors consider such a distributed memory subsystem and study the impact of address space distribution on system performance. For a given application on such a system, we introduce the notion of address assignment quality. We show that this assignment quality metric is strongly correlated with memory subsystem throughput over large regions of the design space. We show this using open loop performance modeling of the memory subsystem, and justify this using a queueing and a Markov chain analysis. Further, we develop a detailed memory subsystem model for a multi-processor simulation system built on the Augmint framework. Using two (highly parallel) applications (matrix multiplication and bubble sort) the authors show that application throughput and assignment quality are strongly correlated over large regions of the design space. We infer that maximization of the assignment quality metric can be a fundamental goal in designing memory subsystems and in developing applications in such systems-on-chip