Multi-core Image processing system using Network on Chip interconnect
Jonathan Joshi, Kedar Karandikar, Sharad Bade, Mandar Bodke, Rohan Adyanthaya, Balkrishan Ahirwal · Conference proceedings · 2007
Real time image processing (I.P.) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time standards call for high speeds , but for data intensive application such as IP algorithms require constant transfer of data between the logic cores. This would need either dedicated connections or additional bus controllers. networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of a bus-based solution. This paper deals with the design and implementation of a multi-core image processing system consisting of different modules. All the cores have been designed targeting real time frame rates. The design has been prototyped on a Virtex II FPGA. The timing results for different video files pertaining to different standards have been presented and processing speeds for standard image sizes have also been given.