Modeling architectural improvements in superscalar processors
Yongxin Zhu, Weng‐Fai Wong · 2000
A model of superscalar processors using a network of Multiple-Class-Multiple-Resource queues is described and studied. In this model, we are able to model and study instruction classes, instruction dependencies, the cache, the branch unit, the decoder unit, the central instruction buffer, the functional units, the retirement buffer, the retirement unit and instruction issue policy in an integrated manner. This model has been verified against measured performance and has shown an average error of 5%.