Novel structure of a user-programmable integrated digital signal processor
R. Geppert · 2005
In this paper we describe a new structure of a digital signal processor peripheral chip which is intended to perform nonrecursive time-domain algorithms at high speed. The restriction to a certain class of algorithms leads to a simple internal structure. Simultaneous execution of basic operations and two banks of input buffer allow for a high through-put rate. A word length of 12 bit for input samples and 16 bit for output will be sufficient for a large number of applications. Loading of program and table data is accomplished via an I2C-type interface. Due to the dedicated task only 23 distinct instructions are necessary for programming the chip. After loading, the chip runs independently indicating end of computations by a two-level interrupt scheme. The chip can be used as stand-alone unit or as microprocessor peripheral.