Low power VLSI architectures for variable-length encoding and decoding
Stephen Molloy, Rajeev Jain · 2005
New low power VLSI architectures are presented for variable-length encoding and decoding. Look-up table partitioning by symbol probability is shown to reduce the total power consumption; the variable-length decoder and encoder are reduced by as much as 66% and 75%, respectively. Design examples for a subband image CODEC are presented with measurements from extracted VLSI layouts.