Translating system specifications to VHDL
Sanjiv M. Narayan, Frank Vahid, Daniel D. Gajski · 1991
Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations. >