VLSI array architecture for Reed-Solomon decoding
B. Arambepola, Somsak Choomchuay · 1991
A new architecture is presented for solving a key equation in a Reed-Solomon decoder. This consists of an array of identical cells. The number of cells can be set to meet a given throughput specification. The architecture is briefly compared with other published systolic architectures for the same problem and its advantages and disadvantages are illustrated.>