Improved Mitchell-based logarithmic multiplier for low-power DSP applications
D.J. Mclaren · 2004
This paper presents a method to improve the accuracy of a logarithmic multiplier, based on Mitchell's algorithms for calculating logarithms and antilogarithms. The method developed offers an area saving of approximately 50% and a power saving of 71% for larger input widths. A FIR filter based on the multiplier is also presented.