Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm
K. Mukaida, Masahiko Takenaka, Naoya Torii, S. Masui · 2004
High-speed and area-efficient Montgomery modular multipliers for RSA algorithm has been developed for digital signature and user authentication in high-speed network and smart card systems. Multiplier-accumulator (MAC) in the developed Montgomery modular multiplier has non-identical multiplicand/multiplier word length. This organization eliminates the bottleneck in memory bandwidth, and enables to use single-port memory for area and power reductions. The developed MAC is faster than the common word length organization due to short critical path. 5,000 digital signature productions/sec is obtained with a three-stage pipelined architecture in 0.18 /spl mu/m CMOS technology.