Optimal temporal partitioning and synthesis for reconfigurable architectures
Meenakshi Kaul, Ranga R. Vemuri · 1998
We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and highlevel synthesis from behavioral specifications destined to be implemented on reconfigurable processors. We present tight linearizations of the NLP model. We present effective variable selection heuristics for a branch and bound solution of the derived linear programming model. We show how tight linearizations combined with good variable selection techniques during branch and bound yield optimal results in relatively short execution times. 1 Introduction Dynamically reconfigurable processors are becoming increasingly viable with the advent of modern fieldprogrammable devices, especially the SRAM-based FPGAs. Execution of hardware computations using reconfigurable processors necessitates a temporal partitioning of the specification. Temporal partitioning divides the specification into a number of specification segments that are destined to be executed one after another on the target processor...