A multi-transputer architecture for parallel logic programs
Prasenjit Biswas, Shyh-Chang Su, D. Wright · 1988
An overview is presented of a scalable, 16-Transputer, mesh-connected architecture that supports a novel message-passing abstract machine model specifically designed for efficient parallel execution of logic programs. An execution model has been developed that is based on message-passing with completely distributed control, with memory references localized to each processor. A demand-driven OR-parallel execution scheme is introduced, which in combination with restricted-AND-parallel execution provides a convenient framework for harnessing explosive parallelism in nonannotated logic programs. The execution mechanism, which is based on the concepts of late binding and selective copying of the uninstantiated variables, eliminates the necessity of long chains for dereferencing, trail stack, and overhead related to backtracking. The implementation of the abstract machine on the multi-transputer testbed, using Occam, is described.>