A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure
T. Yamagata, M. Mihara, Takeshi Hamamoto, Y. Murai, Toshifumi Kobayashi, Michihiro YAMADA, Hiroto Ozaki · IEEE Journal of Solid-State Circuits · 1992
A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mu m/sup 2/) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 mm*12.0 mm using a 0.8- mu m CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, the authors have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns.>