DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache
Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, Jestoni V. Zarsuela, Anastacia P. Ballesil, Joy Alinda Reyes · 2008
Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays, implementation of multiple cores as well as the usage of a cache to increase performance, are necessary. These two solutions were implemented using a 32-bit pipelined DLX microprocessor, resulting to a dual core capable (DCC) DLX with single-level cache in a Uniform Memory Access Architecture type. This project made use of the Shared Cache System divided into an Instruction Cache and a Data Cache to solve processor structural hazards due to coincident instruction and data access.